Integrity and Reliability of Integrated CircuitS (IRIS), Phase III
DARPA is soliciting research proposals for a comprehensive exploration of the effects of extreme physical stresses on wear-out and aging mechanisms in CMOS FETs at 28nm and/or 14nm lithography node. The objective of the IRIS Program Phase III is to explore aging effects in both transistors and transistor interconnects to create predictive models and to test how precisely and rapidly specific wear-out mechanisms can be asserted, for the purposes of accelerating burn-in, aging, and wear-out. See the full DARPA-BAA-15-47 document attached.
General information about this opportunity
Last Known Status
Deleted 03/04/2016 (Archived.)
Program Number
DARPA-BAA-15-47 Federal Agency/Office
Agency: Department of DefenseOffice: ADVANCED RESEARCH PROJECTS AGENCY
Type(s) of Assistance Offered
Cooperative Agreement, Grant, Other, Procurement Contract What is the process for applying and being award this assistance?
Deadlines
09/04/2015 Other Assistance Considerations
Formula and Matching Requirements
This program does not have cost sharing or matching requirements. Who do I contact about this opportunity?
Headquarters Office
Mr. Kerry BernsteinProgram Manager
Website Address
http://www.darpa.mil/work-with-us/opportunities
E-mail Address
DARPA-BAA-15-47@darpa.mil
Financial Information
Obligations
$0.00
